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K4D623238B-GC
64M DDR SDRAM
64Mbit DDR SDRAM
512K x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL (144-Ball FBGA)
Revision 1.4 September 2002
Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 1.4 (Sep. 2002)
K4D623238B-GC
Revision History
Revision 1.4 (September 26, 2002)
* Added tCK(min) and tCK(max) at CL=3 and CL=4
64M DDR SDRAM
Revision 1.3 (March 5, 2002)
* Changed tCK(max) of K4D623238B-GC40 from 7ns to 10ns.
Revision 1.2 (September 1, 2001)
* Added K4D623238B-GL* as a low power part (ICC6=1mA) * Added ICC7 (Operating current at 4bank interleaving) * Added 100MHz@CL2
Revision 1.1 (August 2, 2001)
* Changed tCK(max) of K4D623238B-GC45/-50/-55/-60 from 7ns to 10ns.
Revision 1.0 (June 22, 2001)
* Changed VDD/VDDQ of K4D623238B-GC33 from 2.5V to 2.8V.
Revision 0.4 (April 10,2001) - Preliminary Spec
* Added K4D623238B-GC50 * Added K4D623238B-GC55 * Added K4D623238B-GC60 * Defined tWR_A that means write recovery time @ Auto precharge.
Revision 0.3 (February 10, 2001) - Preliminary
* Changed tDAL of K4D623238B-GC45 from 6tCK to 7tCK.
Revision 0.2 (December 13, 2000) - Target Spec
* Defined Target Specification
Revision 0.0 (November 21, 2000)
-2-
Rev. 1.4 (Sep. 2002)
K4D623238B-GC
512K x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL FEATURES
* 2.5V + 5% power supply for device operation * VDD/VDDQ = 2.8V 5% for -33 * VDD/VDDQ = 2.5V 5% for -60/-55/-50/-45/-40 * SSTL_2 compatible inputs/outputs * 4 banks operation * MRS cycle with address key programs -. Read latency 3,4,5 (clock) -. Burst length (2, 4, 8 and Full page) -. Burst type (sequential & interleave) * Full page burst length for sequential burst type only * Start address of the full page burst should be even * All inputs except data & DM are sampled at the positive going edge of the system clock * Differential clock input * No Wrtie-Interrupted by Read Function * 4 DQS's ( 1DQS / Byte )
64M DDR SDRAM
* Data I/O transactions on both edges of Data strobe * DLL aligns DQ and DQS transitions with Clock transition * Edge aligned data & data strobe output * Center aligned data & data strobe input * DM for write masking only * Auto & Self refresh * 16ms refresh period (2K cycle) * 144-Ball FBGA * Maximum clock frequency up to 300MHz * Maximum data rate up to 600Mbps/pin
ORDERING INFORMATION
Part NO. K4D623238B-GC/L33 K4D623238B-GC/L40 K4D623238B-GC/L45 K4D623238B-GC/L50 K4D623238B-GC/L55 K4D623238B-GC/L60 Max Freq. 300MHz 250MHz 222MHz 200MHz 183MHz 166MHz Max Data Rate 600Mbps/pin 500Mbps/pin 444Mbps/pin 400Mbps/pin 366Mbps/pin 333Mbps/pin SSTL_2 144-Ball FBGA Interface Package
GENERAL DESCRIPTION
FOR 512K x 32Bit x 4 Bank DDR SDRAM
The K4D623238 is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 2 x1,048,976 words by 32 bits, fabricated with SAMSUNG ' high performance CMOS technology. Synchronous features with Data Strobe allow s extremely high performance up to 2.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
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Rev. 1.4 (Sep. 2002)
K4D623238B-GC
PIN CONFIGURATION (Top View)
2 B C D E F G H J K L M N
DQS0 DQ4 DQ6 DQ7 DQ17 DQ19 DQS2 DQ21 DQ22 CAS RAS CS
64M DDR SDRAM
3
DM0 VDDQ DQ5 VDDQ DQ16 DQ18 DM2 DQ20 DQ23 WE NC NC
4
VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD NC BA0
5
DQ3 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS BA1 A0
6
DQ2 DQ1 VSSQ VSSQ
7
DQ0 VDDQ VDD VSS
8
DQ31 VDDQ VDD VSS
9
DQ29 DQ30 VSSQ VSSQ
10
DQ28 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS RFU 2 A7
11
VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD CK A8/AP
12
DM3 VDDQ DQ26 VDDQ DQ15 DQ13 DM1 DQ11 DQ9 NC CK CKE
13
DQS3 DQ27 DQ25 DQ24 DQ14 DQ12 DQS1 DQ10 DQ8 NC MCL VREF
VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS A10 A2 A1 VSS VDD RFU3 A3
VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VDD A9 A4 VSS RFU1 A5 A6
NOTE: 1. RFU1 is reserved for A12 2. RFU2 is reserved for BA2 3. RFU3 is reserved for A11 4. VSS Thermal balls are optional
PIN DESCRIPTION
CK,CK CKE CS RAS CAS WE DQS DM RFU Differential Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Strobe Data Mask Reserved for Future Use BA0, BA1 A0 ~A10 D Q0 ~ DQ31 VDD VSS VDDQ VSSQ NC MCL Bank Select Address Address Input Data Input/Output Power Ground Power for DQ' s Ground for DQ' s No Connection Must Connect Low
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Rev. 1.4 (Sep. 2002)
K4D623238B-GC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol Type Function The differential system clock Input. CK, CK*1 Input
64M DDR SDRAM
All of the inputs are sampled on the rising edge of the clock except D Q's and DM' that are sampled on both edges of the DQS. s Activates the CK signal when high and deactivates the CK signal
CKE
Input
when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS enables the command decoder when low and disabled the com-
CS
Input
mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Data input and output are synchronized with both edge of DQS. DQS0 for DQ0 ~ DQ 7, DQS1 for DQ8 ~ DQ15, DQS2 for DQ16 ~ DQ23, DQS3 for DQ24 ~ DQ 31. Data In mask. Data In is masked by DM Latency=0 when DM is high
CAS
Input
WE
Input
DQS0 ~ DQS3
Input/Output
DM0 ~ DM3
Input
in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ 8 ~ DQ 15, DM2 for D Q16 ~ DQ 23, DM3 for DQ24 ~ DQ 31. Data inputs/Outputs are multiplexed on the same pins. Selects which bank is to be active. Row/Column addresses are multiplexed on the same pins.
DQ 0 ~ DQ 31 BA0, BA1
Input/Output Input
A0 ~ A10
Input
Row addresses : RA0 ~ RA10, Column addresses : CA0 ~ CA7. Column address CA8 is used for auto precharge.
VDD/VSS VDDQ/VSSQ VREF NC/RFU
Power Supply Power Supply Power Supply No connection/ Reserved for future use
Power and ground for the input buffers and core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. Reference voltage for inputs, used for SSTL interface. This pin is recommended to be left "No connection" on the device
MCL
Must Connect Low
Must connect low
*1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin.
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Rev. 1.4 (Sep. 2002)
K4D623238B-GC
BLOCK DIAGRAM (512Kbit x 32I/O x 4 Bank)
64M DDR SDRAM
32
Intput Buffer I/O Control LWE
CK, CK Bank Select
Data Input Register Serial to parallel
64
LDMi
512Kx32 2-bit prefetch Output Buffer S ense AMP Refresh Counter Row Buffer Row Decoder 512Kx32 512Kx32 512Kx32
64 32
x32
DQi
Address Register
CK,CK
ADDR
Column Decoder LRAS LCBR Col. Buffer
Latency & Burst Length Strobe G en. Data Strobe
(DQS0~DQS3)
Programming Register LCKE LRAS LCBR LWE LCAS LWCBR
DLL
CK,CK
LDMi
Timing Register
CK,CK
CKE
CS
RAS
CAS
WE
DMi
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Rev. 1.4 (Sep. 2002)
K4D623238B-GC
FUNCTIONAL DESCRIPTION
* Power-Up Sequence
64M DDR SDRAM
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK), apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order.
Power up & Initialization Sequence
0 CK,CK
tRP
2 Clock min. 2 Clock min.
precharge ALL Banks
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
~ ~
~~ ~
Command
~
precharge ALL Banks
EMRS
MRS DLL Reset
1st Auto Refresh
2nd Auto Refresh
~~ ~~
tRP
tRFC
tRFC
Mode
~ ~
2 Clock min.
Any Command
Register Set
Inputs must be stable for 200us
~ ~
200 Clock min.
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Rev. 1.4 (Sep. 2002)
K4D623238B-GC
MODE REGISTER SET(MRS)
64M DDR SDRAM
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A 0 ~ A 1 0 and BA0, BA1 in the same cycle as CS, RAS, CAS and W E going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A 3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A 8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
RFU
0
RFU
DLL
TM
CAS Latency
BT
Burst Length
Mode Register
DLL A8 0 1 DLL Reset No Yes
Test Mode A7 0 1 mode Normal Test
Burst Type A3 0 1 Type Sequential Interleave Burst Length
CAS Latency BA0 0 1 An ~ A0 MRS EMRS A6 0 0 0 0 * RFU(Reserved for future use) should stay "0" during MRS cycle. 1 1 1 1 MRS Cycle
0 CK, CK Command
NOP Precharge All Banks NOP NOP MRS
A2 Latency Reserved Reserved Reserved 3 4 5 Reserved Reserved 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Burst Type Sequential Reserve 2 4 8 Reserve Reserve Reserve Full page Interleave Reserve 2 4 8 Reserve Reserve Reserve Reserve
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
1
2
3
4
5
6
7
8
NOP
Any Command
NOP
NOP
tRP
tMRD=2 tCK
*1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. -8-
Rev. 1.4 (Sep. 2002)
K4D623238B-GC
EXTENDED MODE REGISTER SET(EMRS)
64M DDR SDRAM
The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A10 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
BA1
BA0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus Extended Mode Register
RFU
1
RFU
D.I.C
RFU
D.I.C
DLL
BA0 0 1
An ~ A0 MRS EMRS
A6 0 0 1 1
A1 0 1 0 1
Output Driver Impedence Control N/A Weak N/A Matched impedance Do not use 60% Do not use 30%
A0 0 1
DLL Enable Enable Disable
* RFU(Reserved for future use) should stay "0" during EMRS cycle.
Figure 7. Extended Mode Register set
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Rev. 1.4 (Sep. 2002)
K4D623238B-GC
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, V OUT V DD VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 2.0 50
64M DDR SDRAM
Unit V V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65C)
Parameter
Device Supply voltage Output Supply voltage Device Supply voltage Output Supply voltage Reference voltage Termination voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current
Symbol
VDD VDDQ VDD VDDQ VREF Vtt VIH VIL VOH VOL IIL IOL
Min
2.375 2.375 2.66 2.66 0.49*V DDQ V REF-0.04 VREF+0.15 -0.30 Vtt+0.76 -5 -5
Typ
2.50 2.50 2.8 2.8 VREF -
Max
2.625 2.625 2.94 2.94 0.51*V DDQ VREF+0.04 VDDQ +0.30 V REF-0.15 Vtt-0.76 5 5
Unit
V V V V V V V V V V uA uA
Note
1,7 1,7 1,8 1,8 2 3 4 5 IOH=-15.2mA IOL=+15.2mA 6 6
Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ , VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. Vtt of the transmitting device must track V REF of the receiving device. 4. VIH(max.)= V DDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V. 7. For -40/-45/-50/-55/-60, VDD/ VDDQ=2.5V + 5% 8. For -33, VDD/V DDQ= 2.8V + 5%
- 10 -
Rev. 1.4 (Sep. 2002)
K4D623238B-GC
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, T A=0 to 65C )
64M DDR SDRAM
Version Parameter Operating Current (One Bank Active) Precharge Standby Current in Power-down mode Precharge Standby Current in Non Power-down mode Active Standby Current power-down mode Active Standby Current in in Non Power-down mode Operating Current ( Burst Mode) Refresh Current Self Refresh Current Symbol Test Condition -33 ICC1 Burst Lenth=2 tRC tRC(min) 470 -40 340 -45 315 -50 290 -55 275 -60 260 mA 1 Unit Note
IOL=0mA, tCC= tC C(min)
CKE VIL(max), tCC= tCC(min) CKE VIH(min), CS VIH(min),
ICC2P ICC2N ICC3P ICC3N
75 155 150 270
65 125 130 220
65 120 130 210
65 115 130 200
65 110 130 190
65 105 130 180
mA mA mA mA
tCC= tCC(min)
CKE VIL(max), tCC= tCC(min) CKE VIH(min), CS VIH(min),
tCC= tCC(min)
IOL=0mA ,tCC = tCC(min), Page Burst, All Banks activated.
ICC4 ICC5 ICC6
900 405 4.5
700 340
650 330
600 320 4
550 310
520 300
mA mA mA mA 2 3 4
tRC tRFC(min)
CKE 0.2V
1
Operating Current ( 4Bank Interleaving) ICC7 Burst Lenth=4 tRC tRC(min)
IOL=0mA, tCC= tC C(min)
1050
850
800
750
700
670
mA
Note : 1. Measured with outputs open. 2. Refresh period is 16ms. 3. K4D623238B-GC* 4. K4D623238B-GL*
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, V DD/ VDDQ =2.5V+ 5%, T A=0 to 65C)
Parameter
Input High (Logic 1) Voltage; DQ Input Low (Logic 0) Voltage; DQ Clock Input Differential Voltage; CK and CK Clock Input Crossing Point Voltage; CK and CK
Symbol
VIH V IL VID VIX
Min
VREF+0.35 0.7 0.5*VDDQ-0.2
Typ
-
Max
VREF-0.35 VDDQ+0.6 0.5*VDDQ +0.2
Unit
V V V V
Note
1 2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
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Rev. 1.4 (Sep. 2002)
K4D623238B-GC
AC OPERATING TEST CONDITIONS
Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition (VDD=2.5V0.125V, TA= 0 to 65C ) Value 0.50*VDDQ 1.5 1.0 VREF+0.35/VREF-0.35 VREF Vtt See Fig.1 Vtt=0.5*V DDQ
64M DDR SDRAM
Unit V V V/ns V V V
Note
RT=50 Output Z0=50 VREF =0.5*VDDQ CLOAD=30pF
(Fig. 1) Output Load Circuit
CAPACITANCE
(VDD=3.3V, TA= 25C, f=1MHz) Symbol
CIN1 CIN2 CIN3 COUT CIN4
Parameter
Input capacitance( CK, CK ) Input capacitance(A0~A10, BA0~BA1) Input capacitance ( CKE, CS, RAS,CAS, WE ) Data & DQS input/output capacitance(DQ 0~ D Q31) Input capacitance(DM0 ~ DM3)
Min
1.0 1.0 1.0 1.0 1.0
Max
5.0 4.0 4.0 6.5 6.5
Unit
pF pF pF pF pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board. Parameter Decoupling Capacitance between VDD and VSS Decoupling Capacitance between VDDQ and VSSQ Symbol CDC1 CDC2 Value 0.1 + 0.01 0.1 + 0.01 Unit uF uF
Note : 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip.
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Rev. 1.4 (Sep. 2002)
K4D623238B-GC
AC CHARACTERISTICS
Parameter
CL=3 CK cycle time CK high level width CL=4 CL=5
64M DDR SDRAM
Symbol
-33
Min
3.3 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.35 0.35 tCLmin or tCHmin tHP0.35 0.55 0.55 0.6 0.6 0.35 1.1 0.6 1.15 0.6 0.6 0.6 -
-40
Min
5.0 7 4.0 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.4 0.4 tCLmin or tCHmin tHP-0.4 0.55 0.55 0.6 0.6 0.4 1.1 0.6 1.15 0.6 0.6 0.6 10
-45
Max Min
5.0 4.5 0.45 0.45 -0.7 -0.7 0.9 0.4 0.8 0 0.3 0.4 0.4 0.4 1.0 1.0 0.45 0.45 tCLmin or tCHmin tHP0.45 0.55 0.55 0.7 0.7 0.45 1.1 0.6 1.2 0.6 0.6 0.6 10
-50
Max Min
5.0
-55
Max
10 0.55 0.55 0.7 0.7 0.45 1.1 0.6 1.2 0.6 0.6 0.6 -
-60
Max
10 0.55 0.55 0.75 0.75 0.5 1.1 0.6 1.25 0.6 0.6 0.6 -
Max
Min
5.5
Min
6.0
Max
10 0.55 0.55 0.75 0.75 0.5 1.1 0.6 1.25 0.6 0.6 0.6 -
Unit Note
ns ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns ns 1 1
tCK
0.45 0.45 -0.7 -0.7 0.9 0.4 0.8 0 0.3 0.4 0.4 0.4 1.0 1.0 0.45 0.45 tCLmin or tCHmin tHP0.45
0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.4 0.4 0.4 1.1 1.1 0.5 0.5 tCLmin or tCHmin tHP-0.5
0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.4 0.4 0.4 1.1 1.1 0.5 0.5 tCLmin or tCHmin tHP-0.5
tCH CK low level width tCL DQS out access time from CK tDQSCK Output access time from CK tAC Data strobe edge to Dout edge tDQSQ Read preamble tRPRE Read postamble tRPST CK to valid DQS-in tDQSS DQS-In setup time tWPRES DQS-in hold time tWPREH DQS write postamble tWPST DQS-In high level width tDQSH DQS-In low level width tDQSL Address and Control input setup tIS Address and Control input hold tIH DQ and DM setup time to DQS tDS DQ and DM hold time to DQS tDH
Clock half period
tHP tQH
Data output hold time from DQS
-
-
-
-
-
-
ns
1
Simplified Timing @ BL=2, CL=4
tCH tCK tCL
0 CK, CK
1
2
3
4
5
6
7
8
CS
tDQSCK
tIS tIH tDQSS tDQSH tDQSL
DQS
tRPRE
tRPST
tWPREH tWPRES
tDQSQ tAC
tDS tDH
DQ
Qa1
Qa2
Db0
Db1
DM
COMMAND READA
WRITEB
- 13 -
Rev. 1.4 (Sep. 2002)
K4D623238B-GC
Note 1 :
64M DDR SDRAM
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL4, BL2)
tHP 0 CK, CK 1 2 3 4 5
CS
DQS tDQSQ(max)
tQH tDQSQ(max) DQ
Qa0 Qa1
COMMAND
READA
- 14 -
Rev. 1.4 (Sep. 2002)
K4D623238B-GC
AC CHARACTERISTICS (I)
Parameter
Row cycle time Refresh row cycle time Row active time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Row active to Row active Last data in to Row precharge @Normal Precharge Last data in to Row precharge @Auto Precharge Last data in to Read command Col. address to Col. address Mode register set cycle time Auto precharge write recovery + Precharge Exit self refresh to read comPower down exit time Refresh interval time
64M DDR SDRAM
-33 Min Max 17 19 12 6 4 5 3 3 3 2 1 2 8 200
1tCK+tIS
Symbol
tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tWR tWR_A tCDLR tCCD tMRD
-40 Min Max 15 17 10 5 3 100K
-45 Min Max 13 15 9 4 2 100K
-50 Min Max 12 14 8 100K
-55 Min Max 12 14 8 100K
-60 Unit Note Min Max 10 tCK 12 tCK
7 100K tCK
100K
-
-
-
4 2 4 2 2 3 2 1 2 7 200
1tCK+tIS
-
4 2 4 2 2 3 2 1 2 7 200
1tCK+tIS
-
3 2 3 2 2 3 2 1 2 6 200
1tCK+tIS
-
tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns us 1 1 1
5 3 3 3 2 1 2 8 200
1tCK+tIS
4 2 3 3 2 1 2 7 200
1tCK+tIS
tDAL
tXSR tPDEX tREF
7.8
7.8
7.8
7.8
7.8
7.8
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
AC CHARACTERISTICS (II)
K4D623238B-GC33 Frequency Cas Latency 333MHz ( 3.3ns ) 5 tRC 17 tRFC 19 tRAS 12 tRCDRD 6 tRCDWR 4 tRP 5 tRRD 3
(Unit : Number of Clock)
tDAL 8
Unit
tCK
K4D623238B-GC40 Frequency Cas Latency 250MHz ( 4.0ns ) 4 222MHz ( 4.5ns ) 4 200MHz ( 5.0ns ) 3 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3
tRC 15 13 12 12 10
tRFC 17 15 14 14 12
tRAS 10 9 8 8 7
tRCDRD 5 4 4 4 3
tRCDWR 3 2 2 2 2
tRP 5 4 4 4 3
tRRD 3 2 2 2 2
tDAL 8 7 7 7 6
Unit
tCK tCK tCK tCK tCK
K4D623238B-GC45 Frequency Cas Latency 222MHz ( 4.5ns ) 4 200MHz ( 5.0ns ) 3 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3
tRC 13 12 12 10
tRFC 15 14 14 12
tRAS 9 8 8 7
tRCDRD 4 4 4 3
tRCDWR 2 2 2 2
tRP 4 4 4 3
tRRD 2 2 2 2
tDAL 7 7 7 6
Unit
tCK tCK tCK tCK
- 15 -
Rev. 1.4 (Sep. 2002)
K4D623238B-GC
64M DDR SDRAM
K4D623238B-GC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3
tRC 12 12 10
tRFC 14 14 12
tRAS 8 8 7
tRCDRD 4 4 3
tRCDWR 2 2 2
tRP 4 4 3
tRRD 2 2 2
tDAL 7 7 6
Unit
tCK tCK tCK
K4D623238B-GC55 Frequency Cas Latency 183MHz ( 5.5ns ) 3 166MHz ( 6.0ns ) 3
tRC 12 10
tRFC 14 12
tRAS 8 7
tRCDRD 4 3
tRCDWR 2 2
tRP 4 3
tRRD 2 2
tDAL 7 6
Unit
tCK tCK
K4D623238B-GC60 Frequency Cas Latency 166MHz ( 6.0ns ) 3
tRC 10
tRFC 12
tRAS 7
tRCDRD 3
tRCDWR 2
tRP 3
tRRD 2
tDAL 6
Unit
tCK
Simplified Timing(2) @ BL=4
0
CK, CK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
B A [ 1 : 0 ] BAa
BAa
BAa
BAa
BAb
BAa
BAb
A8/AP
Ra Ra
Ra
Rb
ADDR (A0~A7, A9,A10)
Ra
Ca
Ra
Rb
Ca
Cb
WE
DQS
DQ
Da0 Da1 Da2 Da3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
DM
COMMAND
ACTIVEA
WRITEA
PRECH
ACTIVEA
ACTIVEB WRITEA
WRITEB
tRCD tRAS tRC tRP tRRD
Normal Write Burst (@ BL=4)
Multi Bank Interleaving Write Burst (@ BL=4)
- 16 -
Rev. 1.4 (Sep. 2002)
K4D623238B-GC
PACKAGE DIMENSIONS (144-Ball FBGA)
A1 INDEX MARK
64M DDR SDRAM
12.0
12.0

0.8x11=8.8
0.10 Max A1 INDEX MARK
0.8
B C D E F G H J K L M N 13 12 11 10 9 8 7 6 5 4 3 2
0.8
0.8x11=8.8
0.45 0.05
0.40
0.35 0.05 1.40 Max 0.40

Unit : mm
- 17 -
Rev. 1.4 (Sep. 2002)

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